An ASIC for fast grey-scale dilation

The design and VLSI implementation of a new ASIC which performs the operation of grey-scale dilation using both image and structuring element threshold decomposition is presented in this paper. The minimum rate of external operations of this ASIC is 30 MPix/sec and it can handle 3 x 3 pixel images and structuring elements of up to 4-bit resolution. The high speed of operation is achieved using the pipelining technique. The ASIC is implemented using a DLM, 1.0 #m, N-well, CMOS process provided by the European Silicon Structures (ES2), and it occupies a silicon area of 5.48 x 5.77 mm = 31.61 mm:. It is intended to be used in machine vision applications, where the need for short processing times is crucial (e.g. robotics and military systems).